------------------------------------------------------
-- HalfAdder
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity HalfAdder is
	port ( I1,I2 : in std_logic;
		SUM, CO : out std_logic);
end HalfAdder;

architecture BEHAVIOR of HalfAdder is
	begin
		SUM <= (I1 xor I2);
		CO <= (I1 and I2);
end BEHAVIOR;


------------------------------------------------------
-- FullAdder
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity FullAdder is
	port( A, B, CIN: in std_logic; S, COUT: out std_logic);
end FullAdder;

architecture behavior of FullAdder is
begin
	S <= A xor B xor CIN;
	COUT <= (A and B) or (B and CIN) or (A and CIN);
end behavior;

architecture structural of FullAdder is
	component HalfAdder
		port (I1, I2: in std_logic; SUM, CO: out std_logic);
	end component;
	signal S1, C1, C2: std_logic;
begin
	HA1 : HalfAdder
		port map (I1 => B, I2 => CIN, CO => C1, SUM => S1);
	HA2 : HalfAdder
		port map (I1 => A, I2 => S1, CO => C2, SUM => S);
	COUT <= C1 xor C2;	
end structural;


------------------------------------------------------
-- Flip flop con reset sincrono ed enable
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity FlipFlop is
	port(	clock, reset, d, enable : in std_logic;
			Q : out std_logic);
end FlipFlop;

architecture behavioral of FlipFlop is
begin
	process(clock)
	begin
		if clock'event and clock='1' then
			if reset='1' then
				Q <= '0';
			elsif enable = '1' then
				Q <= D;
			end if;
		end if;
	end process;
end behavioral;


------------------------------------------------------
-- Flip flop T
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity FlipFlopT is
	port(	clock, T: in std_logic;
			Q : inout std_logic);
end FlipFlopT;

architecture behavioral of FlipFlopT is
begin
	process(clock, T)	
	begin
		if clock'event and clock='1' and T='1' then
			Q <= not Q;
		end if;
	end process;
end behavioral;


------------------------------------------------------
-- Contatore 16 bit unsigned
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity Counter16bit is
	port(	clock, reset: in std_logic;
			value16: out unsigned(15 downto 0));
end Counter16bit;

architecture behavior of Counter16bit is
	signal next_value, value_temp: unsigned(15 downto 0);
begin
	process(clock)
	begin
		if clock'event and clock='1' then
			if reset='1' then
				value_temp <= (others => '0');
			else
				value_temp <= next_value;
			end if;
		end if;
	end process;
	value16 <= (value_temp);
	next_value <= value_temp + conv_unsigned(1,16);
end behavior;



------------------------------------------------------
-- Decontatore x 60
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity DecounterX60 is
	port(	clock, reset, stop: in std_logic;
			value6: out unsigned(5 downto 0));
end DecounterX60;

architecture behavior of DecounterX60 is
	signal next_value, value_temp: unsigned(5 downto 0);
	signal overflow: std_logic;
begin
	process(clock)
	begin
		if clock'event and clock='1' then
			if reset='1' then
				value_temp <= conv_unsigned(60,6);
			elsif overflow='1' then
				value_temp <= conv_unsigned(59,6);
			else
				value_temp <= next_value;
			end if;
		end if;
	end process;
	overflow <= '1' when (value_temp = conv_unsigned(0,6)) else '0';
	value6 <= value_temp;
	next_value <= value_temp - conv_unsigned(1,6) when stop = '0' else value_temp;
end behavior;



------------------------------------------------------
-- Shift register 8 bit (copy'n'paste)
------------------------------------------------------

-- Dichiarazioni
signal enableshift, enableout : std_logic;
signal q, A_int: unsigned(8 downto 0);

-- Shift register
shift_reg: for i in  0 to 7 generate
	ff_i: process(CLOCK)
	begin
		if CLOCK'event and CLOCK='1' then
			if RESET='1' then
				q(i+1) <= '0';
			elsif enableshift = '1' then
				q(i+1) <= q(i);
			end if;
		end if;
	end process;
end generate;
q(0) <= INPUT;

-- Registro d'uscita
process(CLOCK)
begin 
	if CLOCK'event and CLOCK='1' then
		if RESET='1' then
			A_int <= (others => '0');
		elsif enableout = '1' then
			A_int <= q(8 downto 1);
		end if;
	end if;
end process;
OUTPUT <= A_int;



------------------------------------------------------
-- Registri 8 bit per minimo e massimo (copy'n'paste)
------------------------------------------------------

-- Dichiarazioni
signal enablemin, enablemax : std_logic;
signal q, min, max: unsigned(7 downto 0);

-- Minimo
process(CLOCK)
begin 
	if CLOCK'event and CLOCK='1' then
		if RESET='1' then
			min <= (others => '1') ;
		elsif enablemin = '1' then
			min <= q;
		end if;
	end if;
end process;
A_MIN <= min;
enablemin <= '1' when q < min else '0';

-- Massimo
process(CLOCK)
begin 
	if CLOCK'event and CLOCK='1' then
		if RESET='1' then
			max <= (others => '0') ;
		elsif enablemax = '1' then
			max <= q;
		end if;
	end if;
end process;
A_MAX <= max;
enablemax <= '1' when q > max else '0';



------------------------------------------------------
-- Normalizzatore pressione pulsante
-- che può durare più cicli di clock
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity NormButton is
	port (
		BUTTON	: in  std_logic;
		CLOCK	: in  std_logic;
		NORMBUT	: out std_logic
	);	
end NormButton;

architecture behavior of NormButton is
	signal bz : std_logic;	
begin
	process(CLOCK)
	begin
		if (CLOCK'event and CLOCK='1') then
			if BUTTON='1' AND bz='1' then
				NORMBUT <= '1';
				bz <= '0';
			elsif BUTTON='1' AND bz='0' then
				NORMBUT <= '0';
				bz <= '0';
			else
				NORMBUT <= '0';
				bz <= '1';
			end if;
		end if;
	end process;	
end behavior;



------------------------------------------------------
-- Registro accumulatore 8 bit
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity Accumulator8bit is
	port(	clock, reset, enable: in std_logic;
			D8: in unsigned(7 downto 0);
			Q8: out unsigned(7 downto 0));
end Accumulator8bit;

architecture behavior of Accumulator8bit is
	signal tempQ8 : unsigned(7 downto 0);
begin
	process(clock)
	begin
		if clock'event and clock='1' then
			if reset='1' then
				tempQ8 <= (others => '0');
			elsif enable = '1' then
				tempQ8 <= D8 + tempQ8;
			end if;
		end if;
	end process;
	Q8 <= tempQ8;
end behavior;



------------------------------------------------------
-- Logica sequenziale FSM (copy'n'paste)
------------------------------------------------------

	-- Logica sequenziale FSM
	process(CLOCK)
	begin
		if (CLOCK'event and CLOCK='1') then
			if RESET='1' then
				cs <= IDLE;
			else
				cs <= ns;
			end if;
		end if;
	end process;



------------------------------------------------------
-- Logica combinatoria FSM (copy'n'paste)
------------------------------------------------------
	
	-- Logica combinatoria FSM
	process(cs, INPUTS, VARIABLES)
	begin
		VARIABLE1 <= '0';
		VARIABLE2 <= '0';
		case cs is
			-- State 1
			when S1 =>
				VARIABLE1 <= '1';
				if INPUT1 = '1' then
					ns <= S2
				else
					ns <= S1;
				end if;
			-- State 2
			when S2 =>
				VARIABLE2 <= '1';
				if INPUT2 = '1' then
					ns <= S1
				else
					ns <= S2;
				end if;
		end case;
	end process;
	
	

------------------------------------------------------
-- Codifica LEDs a 7 segmenti
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity num_to_DISPLAY is  
  port ( NUM     : in  std_logic_vector(3 downto 0);
         DISPLAY : out std_logic_vector(6 downto 0));
end num_to_DISPLAY;

architecture mio of num_to_DISPLAY is

begin
  process(NUM)
  begin
    case NUM is
      when "0000" => DISPLAY <= "0000010"; --0
      when "0001" => DISPLAY <= "0101111"; --1
      when "0010" => DISPLAY <= "0110000"; --2
      when "0011" => DISPLAY <= "0101000"; --3
      when "0100" => DISPLAY <= "0101101"; --4
      when "0101" => DISPLAY <= "1001000"; --5
      when "0110" => DISPLAY <= "1000000"; --6
      when "0111" => DISPLAY <= "0101011"; --7
      when "1000" => DISPLAY <= "0000000"; --8
      when "1001" => DISPLAY <= "0001000"; --9
      when "1010" => DISPLAY <= "0000001"; --A
      when "1011" => DISPLAY <= "1000100"; --b
      when "1100" => DISPLAY <= "1010011"; --C
      when "1101" => DISPLAY <= "0100100"; --d
      when "1110" => DISPLAY <= "1010000"; --E
      when "1111" => DISPLAY <= "1010001"; --F
      when others => DISPLAY <= "1111111";
    end case;
  end process;
end mio;



------------------------------------------------------
-- Driver seriale a 8 bit
-- (start bit '0', 8-bit data word, NO parity)
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity SERIALDRIVER is
	port(
		CLK			: in std_logic;
		RESET		: in std_logic;
		SERIALLINE	: in std_logic;
		ENABLE		: in std_logic;		
		DATAVALID	: out std_logic;
		PARALLELOUT	: out std_logic_vector(7 downto 0)
	);
	-- T_bit / T_CLK
	constant T_BIT : integer := 9;
	-- T_bit / 2
	constant T_SAMPLE : integer := 4;
	-- Bit counter size
	constant C_SIZE : integer := 4;
end SERIALDRIVER;

architecture rtl of SERIALDRIVER is

	type state is (IDLE, START, B0, B1, B2, B3, B4, B5, B6, B7, ENDS);
	signal cs, ns : state;
	
	signal q : unsigned(8 downto 0);
	signal BitCount : unsigned(C_SIZE-1 downto 0);
	signal NewBit, SampleBit, EndWord, ResCount : std_logic;


begin

--	-- Shift register MSB->LSB
--	shift_reg: for i in 0 to 7 generate 
--		ff_i : process(CLK)
--		begin
--			if CLK'event and CLK='1' then
--				if RESET='1' then
--					q(i+1) <= '0';
--				elsif SampleBit='1' then
--					q(i+1) <= q(i);
--				end if;
--			end if;
--		end process;
--	end generate;
--	q(0) <= SERIALLINE;
	
	-- Shift register LSB->MSB
	shift_reg: for i in 0 to 7 generate 
		ff_i : process(CLK)
		begin
			if CLK'event and CLK='1' then
				if RESET='1' then
					q(i) <= '0';
				elsif SampleBit='1' then
					q(i) <= q(i+1);
				end if;
			end if;
		end process;
	end generate;
	q(8) <= SERIALLINE;	
	
	-- Registro d'uscita
	process(CLK)
	begin
		if CLK'event and CLK='1' then
			if RESET ='1' then
				PARALLELOUT <= (others => '0');
			elsif EndWord = '1' then
				-- MSB->LSB
				--PARALLELOUT <= std_logic_vector(q(8 downto 1));
				-- LSB->MSB
				PARALLELOUT <= std_logic_vector(q(7 downto 0));
			end if;
		end if;
	end process;	

	-- Contatore avanzamento bits
	process(CLK)
	begin
		if (CLK'event and CLK='1') then
			if RESET='1' OR ResCount='1' OR NewBit='1' then
				BitCount <= (others => '0');
			else
				BitCount <= BitCount + conv_unsigned(1, C_SIZE);
			end if;
		end if;
	end process;	
	NewBit <= '1' when BitCount=conv_unsigned(T_BIT-1,C_SIZE) else '0';
	SampleBit <= '1' when BitCount=conv_unsigned(T_SAMPLE,C_SIZE) else '0';
	
	-- Logica sequenziale FSM
	process(CLK)
	begin
		if (CLK'event and CLK='1') then
			if RESET='1' then
				cs <= IDLE;
			else
				cs <= ns;
			end if;
		end if;
	end process;	

	-- Logica combinatoria FSM
	process(cs, SERIALLINE, ENABLE, NewBit)
	begin
		EndWord <= '0';
		ResCount <= '0';
		DATAVALID <= '0';
		case cs is
			-- Idle
			when IDLE =>
				EndWord <= '1';
				ResCount <= '1';
				if SERIALLINE='0' AND ENABLE='1' then
					ns <= START;
				else
					ns <= IDLE;
				end if;
			-- Start bit
			when START =>
				if NewBit='1' then
					ns <= B0;
				else
					ns <= START;
				end if;
			-- Bit 0 (LSB)
			when B0 =>
				if NewBit='1' then
					ns <= B1;
				else
					ns <= B0;
				end if;
			-- Bit 1
			when B1 =>
				if NewBit='1' then
					ns <= B2;
				else
					ns <= B1;
				end if;
			-- Bit 2
			when B2 =>
				if NewBit='1' then
					ns <= B3;
				else
					ns <= B2;
				end if;
			-- Bit 3
			when B3 =>
				if NewBit='1' then
					ns <= B4;
				else
					ns <= B3;
				end if;
			-- Bit 4
			when B4 =>
				if NewBit='1' then
					ns <= B5;
				else
					ns <= B4;
				end if;
			-- Bit 5
			when B5 =>
				if NewBit='1' then
					ns <= B6;
				else
					ns <= B5;
				end if;
			-- Bit 6
			when B6 =>
				if NewBit='1' then
					ns <= B7;
				else
					ns <= B6;
				end if;
			-- Bit 7 (MSB)
			when B7 =>
				if NewBit='1' then
					EndWord <= '1';
					ns <= ENDS;
				else
					ns <= B7;
				end if;
			-- End state
			when ENDS =>
				EndWord <= '1';
				ResCount <= '1';
				DATAVALID <= '1';
				ns <= IDLE;
		end case;
	end process;

end rtl;



------------------------------------------------------
-- Incrementatore semplice (copy'n'paste)
------------------------------------------------------

	process(CLK)
	begin
		if (CLK'event and CLK='1') then
			if RESET='1' OR ResCount='1' then
				Count <= (others => '0');
			elsif CountEn = '1' then
				Count <= Count + conv_unsigned(1, SIZE);
			end if;
		end if;
	end process;